PURPOSE:To attain a short delay time with a small number of elements by constituting a circuit with an inverter, a transfer gate, and a clocked inverter. CONSTITUTION:When an input signal A is '1', '0' and '1' are inputted to gates of transistors TRs Q15 and Q16 constituting a transfer gate 12 respectively and TRs Q15 and Q16 are turned off. Consequently, a signal B is blocked by the gate 12. However, a clocked inverter 14 is set to the operating state because TRs 12 and 13 are turned on together, and the signal B is inverted by the inverter 14. As the result, an inverted signal, the inverse of B is outputted from an output terminal. When the signal A is '0', TRs Q15 and Q16 are turned on together. Consequently, the signal B is transmitted to a connection point N10 through the gate 12. The inverter 14 is set to the non-operating state because TRs Q12 and Q13 are turned off together, and the signal B is blocked by the inverter 14. As the result, the signal B is outputted. When the signal B is '1' or '0', the signal A or, the inverse of A is outputted.