Exclusive or circuit

Abstract

PURPOSE:To attain a short delay time with a small number of elements by constituting a circuit with an inverter, a transfer gate, and a clocked inverter. CONSTITUTION:When an input signal A is '1', '0' and '1' are inputted to gates of transistors TRs Q15 and Q16 constituting a transfer gate 12 respectively and TRs Q15 and Q16 are turned off. Consequently, a signal B is blocked by the gate 12. However, a clocked inverter 14 is set to the operating state because TRs 12 and 13 are turned on together, and the signal B is inverted by the inverter 14. As the result, an inverted signal, the inverse of B is outputted from an output terminal. When the signal A is '0', TRs Q15 and Q16 are turned on together. Consequently, the signal B is transmitted to a connection point N10 through the gate 12. The inverter 14 is set to the non-operating state because TRs Q12 and Q13 are turned off together, and the signal B is blocked by the inverter 14. As the result, the signal B is outputted. When the signal B is '1' or '0', the signal A or, the inverse of A is outputted.

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Cited By (5)

    Publication numberPublication dateAssigneeTitle
    JP-2005354438-ADecember 22, 2005Matsushita Electric Ind Co Ltd, 松下電器産業株式会社タイミング可変装置
    JP-2007013349-AJanuary 18, 2007Renesas Technology Corp, 株式会社ルネサステクノロジ半導体集積回路装置
    JP-2012151662-AAugust 09, 2012Kyushu Institute Of Technology, Tokyo Metropolitan Univ, 公立大学法人首都大学東京, 国立大学法人九州工業大学Ring oscillator
    JP-4515159-B2July 28, 2010パナソニック株式会社タイミング可変装置
    JP-H023144-AJanuary 08, 1990Nec Ic Microcomput Syst LtdSemiconductor memory device